摘要:针对JESD204B协议规定的接收系统的同步问题,提出了一种针对子类1的四字节并行处理实现方案。将数据流中提取的控制信息与数据信息并行处理,简化了接收系统中各种同步的处理过程,同时将电路工作时钟频率从1.25GHz降低到312.5MHz,简化了CMOS实现工艺要求。采用Verilog HDL实现并与XILINX官方IP核进行了对接验证,还在Design Compiler平台采用TSMC 65nm工艺进行综合,结果表明:该设计方案在功能,工作频率等方面均能够满足JESD204B协议要求。
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